Summary

The Dominican Republic declared semiconductor development a “high national priority” via Presidential Decree 324-24 in June 2024. This OECD review, based on aggregate and firm-level economic data combined with nearly 40 stakeholder interviews, assesses what it would take for the DR to actually build a semiconductor and microelectronics ecosystem from scratch. The country has real strengths: a mature free-zone regime, democratic institutions, proximity to the US market, and an existing advanced manufacturing base in medical devices and electronics assembly. The analysis fed directly into the DR’s Estrategia Nacional de Fomento a la Industria de Semiconductores, published in August 2025, which prioritises three segments: passive components and discrete semiconductors, PCB fabrication and assembly, and ATP of mature-generation chips.

Key Insights

1. The DR is starting from zero, and the OECD is realistic about it. No semiconductor firm currently operates in the country. The microelectronics presence is small. The National Semiconductor Strategy sensibly does not aim for wafer fabrication. Instead, it targets passive components, PCBs, and mature-node ATP. This is the right call for a country with a GDP of roughly USD 115 billion and no existing semiconductor workforce. (Exec Summary, p. 8; Box 1.1, p. 14)

2. The OECD explicitly recommends PCB and ATMP/OSAT as the realistic entry point. The report notes that ATP is “relatively labour-intensive and, on average, less capital-, water- and electricity-intensive than front-end manufacturing” and has historically served as the entry point for countries in Latin America and Southeast Asia. In the nearer term, the DR could focus on PCB manufacturing and assembly, where the country’s nascent industry is already beginning to emerge. (p. 54)

3. The free-zone tax regime is extraordinarily generous but poorly targeted. Free-zone firms get a 100% exemption on corporate income tax, import and export duties, municipal taxes, patent taxes, and consular fees for 15 years, with the possibility of renewal. This regime costs the DR 0.6% of GDP in foregone revenue, the second-highest tax expenditure on free zones in Latin America. The problem: these exemptions are generic. A cigar manufacturer gets the same incentive as a semiconductor assembly firm. The OECD recommends complementing the blanket exemptions with targeted incentives for high-value, R&D-intensive sectors. (Table 3.3, p. 56; pp. 56-57)

What This Means for India

The DR’s starting position mirrors several Indian states. Not India as a whole, which has a large chip design ecosystem and 10 approved semiconductor manufacturing projects under the ISM scheme, but specific states. Think of Odisha, Assam, Jharkhand, or Madhya Pradesh: states with industrial ambitions but no existing semiconductor presence, limited technical workforce in this domain, and a need for a realistic entry strategy. The OECD’s five-point diagnostic (institutional framework, free-zone regime, business environment, science and innovation, infrastructure) is a ready-made checklist for any Indian state government thinking about where to start.

The 100% tax exemption is not India’s path. The DR offers a blanket 15-year holiday on essentially every tax that exists. India’s GST regime, the sunset of SEZ tax benefits, and the broader constraints of fiscal federalism make this approach impossible to replicate. But that does not make the DR’s experience irrelevant. The OECD’s own critique, that the exemptions are too generic and should be complemented with targeted incentives for capital investment and R&D, is precisely the direction India’s ISM scheme has already taken. Indian states could study how DR’s free-zone administrative process works (8 processes, 47 requirements, 24 weeks to set up) and benchmark their own single-window clearance timelines against it.

The R&D gap is a warning India should take seriously. The DR spends between 0.01% and 0.03% of GDP on R&D. It has filed exactly 2 semiconductor-related PCT patents in 23 years. FONDOCYT, the sole public R&D fund, has seen half its allocated money delayed or never disbursed. This is what happens when a country builds manufacturing capacity without a parallel investment in research and innovation. India’s situation is vastly better on this front, with a large chip design ecosystem and thousands of semiconductor patents. But at the state level, the risk is real: states racing to set up OSAT plants and semiconductor training centres may treat R&D as a second-order priority. The DR experience shows that without deliberate R&D policy, even two decades of free-zone manufacturing does not produce domestic technological capability. Indian states should build R&D incentives (tax credits, industry-academia grants, innovation clusters) into their semiconductor strategies from day one, not as an afterthought.

The workforce model deserves attention, especially on gender. The DR has about 40,000 workers in advanced manufacturing, with 45% being women. That female participation rate is remarkably high. India’s semiconductor workforce is overwhelmingly male, and the broader manufacturing sector does not come close to 45% female participation. The DR achieved this partly because its free-zone model attracted industries like medical devices and textiles that already had high female employment, and the workforce carried over into higher-value manufacturing. On the training front, the DR’s approach is familiar: a Purdue University MoU for research and academic exchange (signed 2024), and Keysight Technologies opening a Centre of Excellence at INTEC in Santo Domingo (2025). Indian states setting up semiconductor training programmes through ITIs and new institutes should study these partnerships rather than relying on standalone government training programmes disconnected from industry.

Infrastructure constraints are shared, and the DR is worse off. The DR loses 37% of generated electricity during distribution, the highest in the LAC region. Its public grid averages 19 interruptions and 24 blackout hours per month. Free-zone firms bypass this by operating as non-regulated electricity users, but the grid unreliability makes it harder for local suppliers outside the free zones to participate in semiconductor supply chains. India’s grid is significantly more reliable on average, but the specific sites chosen for semiconductor clusters (Dholera, Sanand, candidate sites in Telangana and Tamil Nadu) face their own water stress and power reliability questions. The DR’s experience reinforces what I have argued elsewhere: utility infrastructure is a first-order semiconductor siting constraint, not a background assumption.

Data Extracted

Source

OECD (2026), Review of the Dominican Republic’s Enabling Environment for the Semiconductor and Microelectronics Industries, OECD Publishing, Paris, https://doi.org/10.1787/0b35b5a6-en.

Read the full report at OECD →

Summary

This OECD review examines Mexico’s positioning in global semiconductor value chains, focusing on the nearshoring opportunity created by US-China tech decoupling. It assesses Mexico’s current role (primarily in assembly and test), identifies binding constraints (skilled workforce, water and power infrastructure, supplier ecosystem depth), and sets out policy options for moving up the value chain.

⚠️ Seed content — verify against actual OECD report. This page is a scaffold. Replace the placeholder insights below with your own notes after reading the full OECD publication.

Key Insights

1. Nearshoring is a back-end story, not a fab story. Mexico’s realistic near-term opportunity is in assembly, packaging, and testing — not in front-end fabs — because of the capital and talent gap. (placeholder)

2. Workforce is the binding constraint. The report flags a shortfall of semiconductor-specific technical skills at the mid-level (technician, process engineer) — not just PhD shortages. (placeholder)

3. Supplier ecosystem depth matters more than tax incentives. Fabless and OSAT investors repeatedly cited local supplier shallowness as a bigger deterrent than marginal tax rates. (placeholder)

4. Water and reliable power are pre-conditions, not nice-to-haves. Several of Mexico’s candidate regions face water stress and grid reliability issues that would disqualify them for semiconductor investment. (placeholder)

5. Regional clusters outperform dispersed incentives. The report recommends concentrating support in 1-2 regional clusters rather than spreading investment incentives thinly. (placeholder)

What This Means for India

India’s ISM scheme shares Mexico’s central bet: that OSAT and assembly, not leading-edge fabs, are the realistic near-term entry point into the global semiconductor value chain. The OECD’s Mexico diagnosis is therefore a direct mirror.

First, the workforce warning is the most portable insight. India’s semiconductor strategy has concentrated on design talent (where India is already a global supplier to fabless firms) and capital subsidies for fabs. The OECD’s Mexico report points to a middle-skill gap — technicians, process engineers, equipment maintenance — that India’s Semiconductor Mission has only recently begun to address through the new semiconductor-specific ITIs. The Mexico experience suggests this is the risk most likely to bite first.

Second, the supplier ecosystem argument challenges the “build one big fab” mental model. India’s Dholera and Sanand investments have attracted anchor investors, but the OECD’s Mexico review suggests the second-order question — will a supplier ecosystem of gases, chemicals, equipment servicing, and specialty materials develop around these anchors? — is where value is either captured or lost. Mexico hasn’t cracked this; India’s strategy needs an explicit supplier-ecosystem component, not just anchor-investor incentives.

Third, the regional cluster recommendation is a caution against the politics of dispersal. India has already spread ISM-approved projects across four states. The OECD’s finding that concentration beats dispersal in Mexico’s case should inform how future ISM rounds are allocated.

Data Extracted

Populate this section with quantitative data from the actual OECD report. Include cross-country comparisons where possible and highlight India’s row.

Source

OECD, Promoting the Development of the Semiconductor Ecosystem in Mexico.

Read the full report at OECD →

Summary

OECD Science, Technology and Industry Policy Paper No. 188 — the first publication from the OECD Semiconductor Production Database, which applies the taxonomy developed in Chips, Nodes and Wafers (OECD, 2024) to actual fab-level data. It maps global wafer fabrication capacity by economy, process node density, chip type, ownership structure, and business model, using data from SEMI’s World Fab Watch (Q3 2025), TechInsights’ 300mm Watch, and the Semico Fab Database, augmented with desk research. The database covers 1,433 fabs of which 1,326 are in-production as of September 2025.

Key Insights

1. Five economies hold 87% of global in-production capacity. China, Chinese Taipei, Korea, Japan, and the United States together account for nearly 90% of installed wafer fab capacity as of September 2025. Within these economies, concentration compounds further: the ten largest semiconductor companies account for around half of total global production capacity. (p. 7, 27)

2. China dominates every chip type category relevant to India. China and Chinese Taipei are the only two economies in the top-five across all six chip type categories (power, analog, mature logic, advanced logic, commodity memory, specialty memory). China leads in power/discrete (6.28M WSPM), analog (3.64M WSPM), and mature logic (4.23M WSPM) — the exact three segments where India’s upcoming fabs will operate. (Figure 4, p. 18)

3. India is the largest upcoming capacity contributor in Rest of World. Figure 3 lists Tata Electronics (and, in the September 2025 data vintage, Vedanta) as the top upcoming capacity-generating companies for the Rest of World category. RoW as a whole grows +22% from upcoming fabs. This is the first time India enters the OECD’s Semiconductor Production Database. (Figure 3, p. 16)

4. China’s upcoming mature-node expansion alone exceeds India’s entire planned capacity 16x. China is adding 0.81M WSPM in upcoming mature logic capacity. India’s Tata/PSMC target is ~0.05M WSPM. Geography is not diversifying — upcoming investments are concentrated in the same five large producing economies. (Figure 3, 5, p. 16, 19–20)

What This Means for India

India’s fab entry is sovereign capability-building, not commercial competition. Tata/PSMC at 50,000 wspm (~0.05M WSPM) is entering a mature-logic segment where China already has 4.23M WSPM in production and another 0.81M WSPM under construction. There is no commercial story here. The right frame is supply chain security for automotive, defence, and telecom — a domestic anchor, not a market-share play. ISM communications that imply India is “catching up” in global chip manufacturing miss the point by an order of magnitude. Catching up is not the goal; having any capacity at all is.

The Vedanta listing is a stale data artefact. The OECD database (September 2025 snapshot) lists Vedanta alongside Tata in the upcoming RoW category. This reflects plans that were active at the time of data collection. Vedanta’s fab project has since been discontinued — the joint venture with Foxconn collapsed in 2023, and no credible replacement has materialised. India’s realistic upcoming front-end fab capacity is Tata/PSMC only. Anyone citing this paper’s RoW numbers for India should halve the Vedanta contribution.

China’s mature-node dominance may be even larger than shown. The OECD explicitly flags that Chinese companies have limited incentive to disclose production capabilities under geopolitical scrutiny. Commercial datasets update Chinese fab records only when public media reports new investments. The paper warns that actual wafer fabrication capacity in China is “likely higher than estimated.” If so, the already-overwhelming gap between China and India in mature-node logic is understated. (p. 35)

India has a narrow window to push the OECD for back-end statistics. This paper is front-end only — it excludes OSAT, ATMP, and advanced packaging. India’s ISM wins (Micron Sanand ATMP, CG Semi OSAT) are statistically invisible. The OECD has signalled a back-end extension is coming. MeitY and ISA have a direct interest in shaping how OSAT capacity is classified — by package type, chip category, or technology tier. India’s ISM data is already being collected; mapping it to the OECD taxonomy before the next revision cycle costs almost nothing. Not doing so means India’s genuine manufacturing wins remain invisible in the framework that Washington, Brussels, and Tokyo use for supply-chain risk analysis.

Charts

Data Extracted

In-production wafer capacity by chip type — top economies (Figure 4, p. 18; values in millions WSPM in 8” equivalents)

Note: India values are targets from planned/under-construction fabs, not in-production capacity.

Upcoming capacity growth by economy (Figure 3, p. 16; % growth over in-production base)

†Vedanta listed in OECD September 2025 data vintage; fab project has since been discontinued.

Feature size distribution — five largest economies (Figure 1, p. 13; shares are approximate from chart)

Source

OECD (2025), The chip landscape: Geographical distribution of wafer fabrication capacity, OECD Science, Technology and Industry Policy Papers, No. 188, OECD Publishing, Paris, https://doi.org/10.1787/02dbd028-en.

Read the full paper at OECD →

Summary

OECD Science, Technology and Industry Policy Paper No. 182. The paper advances the OECD’s multi-year effort to measure the semiconductor value chain — building on the 2023 Vulnerabilities in the Semiconductor Supply Chain working paper and the 2024 Chips, Nodes and Wafers taxonomy — by explicitly mapping dependencies and identifying vulnerabilities across the three core stages: chip design, wafer foundry, and assembly/test/packaging (ATP).

⚠️ Seed content — replace with detailed extracts after reading the full paper.

Key Insights

1. Dependency is not a single number. The paper distinguishes multiple dimensions of dependency: concentration of suppliers, geographic concentration, technological concentration (node-specific), and firm-level concentration. A country can be well-diversified on one dimension and dangerously concentrated on another.

2. The design stage has different dependencies from the foundry and ATP stages. Design depends heavily on EDA tools and IP from a small number of firms (Synopsys, Cadence, Mentor/Siemens EDA, Arm). Foundry depends on equipment (ASML, AMAT, Tokyo Electron, Lam, KLA) and materials. ATP has its own, often underappreciated, dependencies.

3. Equipment dependencies may be the tightest of all. ASML’s near-monopoly on EUV lithography is the best-known case; the report likely quantifies several similar single-supplier chokepoints for less-discussed equipment categories.

4. Materials dependencies are underrated. Noble gases (neon, xenon), specialty chemicals, photoresists, and substrates exhibit concentration patterns that are often more acute than equipment dependencies — and the 2022 Russia-Ukraine war’s neon gas squeeze was an early warning.

5. The policy toolkit for reducing dependencies is limited. The paper is typically cautious about blunt instruments (tariffs, export controls, domestic-content mandates) and points instead toward diversification incentives, stockpiling, and multilateral coordination.

What This Means for India

First, this paper is the right starting point for India’s supply-chain resilience conversation. Indian policy debates about semiconductor resilience too often default to “build everything domestically”, which is neither feasible nor desirable at India’s current scale. The OECD’s more sophisticated framework — mapping which dependencies are actually risky (single-source, single-country, no substitutes) versus which are benign (many competitive suppliers) — is the lens Indian policymakers should adopt.

Second, India’s own dependencies are worth auditing explicitly. India is almost entirely import-dependent for: semiconductor manufacturing equipment, photoresists, specialty gases, high-purity chemicals, substrate materials, wafers, and leading-edge EDA tool licences. For OSAT and ATMP, add dependencies on lead frames, bonding wires, and molding compounds. An Indian institution (Takshashila, NITI Aayog, a state SIDC) should produce an India-specific dependency audit using the OECD’s methodology. This would be a much more useful input to policy than the current vague resilience rhetoric.

Third, the “design has different dependencies from fab” point is critical for Indian industrial policy design. India is a global force in chip design but a negligible one in fabrication. If the main near-term resilience objective is to secure India’s existing design industry against chokepoints, the policy levers (EDA-tool sovereignty, IP access, talent retention) are completely different from the levers for securing a future manufacturing base (equipment, materials, utilities). The OECD framework makes it easier to keep these two objectives distinct, which Indian policy conversations routinely conflate.

Fourth, the materials dependency insight should inform ISM 2.0’s scope. If specialty gases and chemicals are the tightest chokepoints, India’s industrial policy should not stop at fab and OSAT incentives — it should extend to specialty chemicals, industrial gases, and substrate materials. Several of these are plausibly within India’s existing chemical-industry capabilities with a modest policy push. This is a concrete expansion of ISM scope the OECD analysis would support.

Data Extracted

Pull concentration metrics (Herfindahl indices, top-3 supplier shares) for each value-chain stage and populate data/datapoints.yml. Particularly useful for cross-country comparison: India’s exposure to each chokepoint category.

Source

OECD (2025), Mapping the Semiconductor Value Chain: Working Towards Identifying Dependencies and Vulnerabilities, OECD Science, Technology and Industry Policy Papers, No. 182, OECD Publishing, Paris, https://doi.org/10.1787/4154cdbf-en.

Read the full paper at OECD →

Summary

This OECD country review examines the opportunities and challenges of the Philippine semiconductor ecosystem, with a specific focus on assembly, testing, and packaging (ATP). It combines quantitative and policy analysis — covering infrastructure, human capital, and global value chain integration — and offers concrete recommendations across business environment, R&D, technology, and workforce development. A companion OECD blog post distilled seven headline strategies.

The Philippines is the ninth-largest chip exporter globally, and semiconductors are the single largest component of its exports. Unlike Mexico or the Dominican Republic, the Philippines is an established player being asked how to grow and move up the value chain — not a late entrant being asked how to break in.

⚠️ Seed content — replace with detailed extracts after reading the full report.

Key Insights

1. ATP is the anchor, but the report asks whether ATP-only is a dead end. The Philippines’ position in semiconductors is overwhelmingly in assembly, test, and packaging. The OECD’s review asks — politely but pointedly — whether this specialisation is a durable platform or a ceiling.

2. Workforce is a recurring theme, as in every OECD country review. The report highlights the need for industry-academia partnerships and international collaboration to scale up workforce development. (extract specific recommendations)

3. Business environment constraints are separable from incentive-policy constraints. The report distinguishes the friction of doing business in the Philippines (regulatory, logistical, administrative) from the size of fiscal incentives — and is clear that fixing the former matters more than enlarging the latter.

4. R&D and technology intensity are flagged as the main constraints to moving up. The Philippines has not translated its ATP volume into R&D investment or domestic technology development.

5. International collaboration is treated as a substitute for scale. The OECD recommends that the Philippines lean into partnerships (likely with Japan, Korea, the US, and other OECD economies) as a way to access technology and markets the country cannot develop on its own.

What This Means for India

First, the Philippines is the most direct comparator India has. Mexico and the Dominican Republic are useful analogues at the margins. The Philippines is a structural twin: large population, English-speaking, democratic, middle-income, with an established OSAT/ATP presence (the India–Philippines comparison on ATP has been made by Indian industry associations for years). Every page of this report should be read with the question: does this also apply to India, and if not, why not?

Second, the “is ATP-only a dead end?” question is the one India must confront. India’s ISM scheme bet heavily on OSAT/ATP as the realistic entry. The OECD’s Philippines review is a 2-decade-later check on whether the bet compounds into something more — or remains a trapped specialisation that delivers exports and jobs without moving India up the value chain. The answer from the Philippines appears to be “moving up requires deliberate action on R&D and technology” — a piece of policy intelligence India’s ISM 2.0 conversation desperately needs.

Third, the workforce + academia + international collaboration playbook maps onto India’s own gap. India’s IIT and NIT system produces world-class design engineers but very few fab-floor technicians, process engineers, or packaging-specialty operators. The Philippines’ approach of tying workforce development to industry partnerships and international collaboration is directly borrowable for India’s ITI system and its semiconductor-specific training programmes.

Fourth, the business-environment point is a quiet rebuke that applies to India too. India’s ISM debates over-index on incentive size and under-index on the texture of doing business (permits, customs, logistics, power reliability, water, contract enforcement). The OECD’s Philippines review is a reminder that for footloose global semiconductor investors, the friction of operating matters more than the headline subsidy number.

Fifth, the international collaboration recommendation is directly applicable to India. India already has semiconductor MoUs with the US, Japan, the EU, Singapore, and others. The Philippines review gives the argument for why these MoUs need to be converted into operational technology-transfer and joint-training programmes — not kept as diplomatic symbolism.

Data Extracted

Pull the Philippine baseline metrics and populate data/datapoints.yml for direct India-Philippines comparison.

Source

OECD (2024), Promoting the Growth of the Semiconductor Ecosystem in the Philippines, OECD Publishing, Paris, https://doi.org/10.1787/01497fea-en.

Companion piece: OECD blog (January 2025), 7 strategies to strengthen the semiconductor ecosystem in the Philippines.

Read the full report at OECD →

Summary

A 38-page OECD Science, Technology and Industry Policy Paper that proposes a comprehensive framework for classifying semiconductors and their production facilities. The taxonomy covers front-end wafer fabs using three dimensions: (i) general company and plant information (location, ownership, operational status, start year, business model), (ii) capability (chip types produced, feature size, wafer size, transistor type, process technologies, semiconductor material), and (iii) capacity (wafer starts per month, cleanroom size). The paper sets itself up explicitly as the basis for the OECD’s Semiconductor Production Database — the infrastructure that later reports like The Chip Landscape (2025) build on.

Key Insights

1. The semiconductor taxonomy problem is real and largely unsolved. Public semiconductor statistics have historically mixed nodes, chip types, wafer sizes, and facility types in incompatible ways. The OECD’s proposed taxonomy is a first attempt to standardise what a “fab record” looks like across countries. Without it, cross-country and time-series comparisons remain unreliable. (pp. 6–8)

2. The taxonomy is three-layered: plant information, capability, and capacity. Each layer has specific fields (see Data Extracted below). The capability layer is the richest — it includes not just node size but transistor architecture, process technologies, and semiconductor material, all of which matter for understanding substitutability between fabs. (Figure 7, p. 27)

3. Chip substitutability and fab substitutability are the two supply-chain risk concepts the taxonomy is designed to support. Chip substitutability asks whether a specific chip in an end-product can be swapped for another. Fab substitutability asks whether a chip’s production can shift to another plant with minimal equipment changes. Neither question can be answered without knowing a fab’s detailed capability profile. (p. 11)

4. The taxonomy is intentionally front-end focused first. Back-end facilities — OSAT, ATMP, advanced packaging — are acknowledged as an important future extension but are not covered in this version. This is a significant gap for countries like India whose manufacturing footprint is currently concentrated in back-end processes. The paper also notes that advanced packaging is actively blurring this boundary: interposers for CoWoS-type packaging must be fabricated at front-end fabs, and TSMC already incorporates electroplating and related back-end equipment into its fabs for this reason. Future taxonomy revisions will need to account for this. (pp. 9–10)

5. FinFET is reaching its limits; gate-all-around (GAAFET) is the next transistor generation. The paper notes FinFETs are “currently reaching the limit of how high fins can go and how many fins can be placed side by side.” GAA-FETs use stacked nanosheets so the gate surrounds the channel on all four sides — further reducing leakage and increasing drive current. IEEE’s International Roadmap for Devices and Systems forecasts logic chips scaling to below 1nm by the 2030s using GAAFET and 3D integration. India’s Tata/PSMC fab spans 28nm to 110nm — planar CMOS nodes, well before FinFET territory. India is entering front-end manufacturing at the current-generation to mature-node tier. That’s a defensible strategic position — mature nodes are commercially critical and far less capital-intensive than leading edge — but ISM communications should say so plainly rather than letting the word “fab” imply technological parity with TSMC or Samsung. (pp. 16–17)

What This Means for India

India has exactly two front-end wafer fabs under construction as of 2026, and both can be fully characterised using the OECD taxonomy. The first is Tata Electronics + PSMC in Dholera, Gujarat — a foundry, under construction, targeting first chips in late 2026. Chip type is logic; feature size spans 28nm to 110nm nodes; transistor architecture is planar CMOS (28nm is a pre-FinFET node); material is silicon; target capacity is approximately 50,000 wafer starts per month. When it begins production, India will appear in the OECD’s Semiconductor Production Database as a front-end logic manufacturer for the first time.

The second is SiCSem in Bhubaneswar, Odisha — a compound semiconductor fab being built in partnership with Clas-SiC Wafer Fab (Scotland). Chip type is power/analog; material is silicon carbide (SiC); applications target electric vehicles, defence equipment, railways, and fast-charging infrastructure. Target capacity is approximately 60,000 wafers per year (~5,000 wafer starts per month). This is India’s first SiC device fab, and it maps cleanly to the OECD taxonomy’s compound semiconductor material category.

Everything else in India’s ISM portfolio is back-end, and none of it appears in this taxonomy. Micron’s Sanand ATMP plant (inaugurated February 2026) and CG Semi’s OSAT facility (G1 operational since August 2025) are the most-publicised Indian semiconductor projects of recent years. They are not counted. The OECD’s front-end-first taxonomy makes India look smaller than it is in the global packaging and assembly landscape. This is not a quibble — it matters for how supply-chain risk analyses, subsidy benchmarks, and resilience assessments are conducted in Washington, Brussels, and Tokyo.

India should have a reviewer in the next taxonomy revision round. The OECD has signalled that a back-end extension is coming. MeitY and ISA have a clear interest in shaping how OSAT and ATMP are classified — by package type, chip category, or technology tier. India’s ISM scheme already collects data from approved projects. Mapping that data to the OECD taxonomy costs very little. Not doing so means billions in investment remain statistically invisible.

Indian think tanks and researchers should treat this taxonomy as the reference vocabulary. Any India-focused semiconductor tracking effort — fab trackers, state-level investment databases, ISM dashboards — should explicitly map its categories to the OECD framework. That makes India-specific work interoperable with international benchmarks and significantly more useful to policymakers benchmarking India against Taiwan, Malaysia, or Vietnam.

Data Extracted

OECD’s proposed taxonomy for front-end wafer fabs (Figure 7, p. 27)

India’s front-end wafer fabs mapped to OECD taxonomy (back-end ATMP/OSAT projects excluded — they fall outside this taxonomy)

Source

OECD (2024), Chips, Nodes and Wafers: A Taxonomy for Semiconductor Data Collection, OECD Science, Technology and Industry Policy Papers, OECD Publishing, Paris, https://doi.org/10.1787/f68de895-en.

Companion OECD blog: Speaking the same chip language: why a shared semiconductor taxonomy matters for global co-operation and supply chain resilience (November 2024).

Read the full paper at OECD →

Summary

Haramboure, A., et al. (2023), Vulnerabilities in the Semiconductor Supply Chain, OECD Science, Technology and Industry Working Papers, No. 2023/05. The paper maps cross-country and cross-sectoral dependencies in the semiconductor value chain using new OECD Inter-Country Input-Output (ICIO) data that, for the first time, separate the semiconductor industry from the wider computer and electronics value chain. It covers the three core semiconductor manufacturing stages — chip design, wafer foundry, and assembly, test and packaging (ATP) — and analyses the downstream industries that depend on semiconductors as critical inputs (information and communications, motor vehicles, and others).

The paper’s policy conclusion is measured: semiconductor shortages can produce large ripple effects through downstream industries, but the policy options to reduce these vulnerabilities must be weighed against the efficiency benefits of global sourcing.

⚠️ Seed content — replace with detailed extracts after reading the full paper.

Key Insights

1. The ICIO innovation is the point. Until this paper, semiconductor-specific input-output data did not exist in standard OECD datasets — semiconductors were bundled into a broader “computer, electronic and optical products” category that masked the very dependencies policymakers wanted to see. The paper’s methodological contribution is the unbundling.

2. Downstream dependence is bigger than commonly recognised. Motor vehicles, ICT, and several machinery sectors are far more dependent on semiconductor inputs than their finished-goods export values would suggest. The paper likely quantifies this exposure explicitly.

3. Cross-country dependencies are highly asymmetric. The paper maps which countries are semiconductor net suppliers (Taiwan, South Korea, US, Japan) and which are net consumers — and how specific the dependencies are.

4. The three stages (design, foundry, ATP) have different dependency profiles. Later OECD work — particularly the 2025 Mapping the Semiconductor Value Chain policy paper — builds directly on this stage-specific framing.

5. Policy options are presented with caution. The paper discusses diversification, stockpiling, and international cooperation, but is explicit that cost-benefit analysis matters. Blunt self-sufficiency strategies are neither analytically supported nor likely to be efficient.

What This Means for India

First, this paper is the right prior for India’s supply-chain resilience conversation. Indian policy debates on semiconductor resilience tend to operate with vivid anecdotes (the 2021 auto chip shortage, the Russia-Ukraine neon squeeze) and sweeping aspirations (atmanirbhar, self-reliance). This paper forces a more quantitative framing: how exposed is India actually, to which stages, through which downstream industries? The answer is that India’s exposure is heaviest in ICT equipment, automotive, and increasingly defence — and the policy implication is segment-specific rather than system-wide.

Second, India’s position in the global ICIO picture is a mirror worth holding up. India is a significant consumer of imported semiconductors and a modest exporter of semiconductor design services (through captives of global IDMs and fabless firms). It is not, as of this paper’s snapshot, a significant manufacturer. Any Indian policymaker making claims about India’s semiconductor standing should know exactly where India sits in the OECD’s ICIO tables and how that has (or has not) changed since 2023.

Third, the “downstream dependence is bigger than commonly recognised” insight is the most important one for India’s automotive sector. India’s auto industry — already the third-largest in the world by production — is deeply exposed to semiconductor inputs. The 2021-22 auto chip shortage cost Indian OEMs significant production losses. The OECD’s quantitative framework is the right tool for asking which segments of the Indian auto value chain are most exposed, and what policy responses (domestic ATP, preferential allocation agreements with foreign fabs, strategic stockpiling) are worth the cost.

Fourth, the paper’s caution on blunt policies is a useful corrective to Indian industrial policy reflexes. India has a tradition of reaching for domestic-content mandates, import restrictions, and export bans when supply chains look risky. This paper is a careful argument that such instruments rarely produce the intended resilience and often sacrifice efficiency. An Indian ISM 2.0 conversation should read this carefully before reaching for such tools.

Fifth, this is the paper to cite when resisting unrealistic self-sufficiency demands. Indian political discourse occasionally demands complete semiconductor self-sufficiency. The OECD’s analysis is the best-available technocratic rebuttal: quantified, cautious, and grounded in data rather than assertion.

Data Extracted

Pull India-specific ICIO figures if present — net semiconductor import dependency, exposure by downstream sector, concentration metrics.

Source

Haramboure, A., et al. (2023), Vulnerabilities in the Semiconductor Supply Chain, OECD Science, Technology and Industry Working Papers, No. 2023/05, OECD Publishing, Paris, https://doi.org/10.1787/6bed616f-en.

Read the full paper at OECD →