Review of the Dominican Republic’s Enabling Environment for the Semiconductor and Microelectronics Industries
📄 Read at OECD ↗Country Review · Mar 2026 · 116 pp
Summary
The Dominican Republic declared semiconductor development a “high national priority” via Presidential Decree 324-24 in June 2024. This OECD review, based on aggregate and firm-level economic data combined with nearly 40 stakeholder interviews, assesses what it would take for the DR to actually build a semiconductor and microelectronics ecosystem from scratch. The country has real strengths: a mature free-zone regime, democratic institutions, proximity to the US market, and an existing advanced manufacturing base in medical devices and electronics assembly. The analysis fed directly into the DR’s Estrategia Nacional de Fomento a la Industria de Semiconductores, published in August 2025, which prioritises three segments: passive components and discrete semiconductors, PCB fabrication and assembly, and ATP of mature-generation chips.
Key Insights
The DR is starting from zero, and the OECD is realistic about it. No semiconductor firm currently operates in the country. The microelectronics presence is small. The National Semiconductor Strategy sensibly does not aim for wafer fabrication. Instead, it targets passive components, PCBs, and mature-node ATP. This is the right call for a country with a GDP of roughly USD 115 billion and no existing semiconductor workforce. (Exec Summary, p. 8; Box 1.1, p. 14)
The OECD explicitly recommends PCB and ATMP/OSAT as the realistic entry point. The report notes that ATP is “relatively labour-intensive and, on average, less capital-, water- and electricity-intensive than front-end manufacturing” and has historically served as the entry point for countries in Latin America and Southeast Asia. In the nearer term, the DR could focus on PCB manufacturing and assembly, where the country’s nascent industry is already beginning to emerge. (p. 54)
The free-zone tax regime is extraordinarily generous but poorly targeted. Free-zone firms get a 100% exemption on corporate income tax, import and export duties, municipal taxes, patent taxes, and consular fees for 15 years, with the possibility of renewal. This regime costs the DR 0.6% of GDP in foregone revenue, the second-highest tax expenditure on free zones in Latin America. The problem: these exemptions are generic. A cigar manufacturer gets the same incentive as a semiconductor assembly firm. The OECD recommends complementing the blanket exemptions with targeted incentives for high-value, R&D-intensive sectors. (Table 3.3, p. 56; pp. 56-57)
What This Means for India
The DR’s starting position mirrors several Indian states. Not India as a whole, which has a large chip design ecosystem and 10 approved semiconductor manufacturing projects under the ISM scheme, but specific states. Think of Odisha, Assam, Jharkhand, or Madhya Pradesh: states with industrial ambitions but no existing semiconductor presence, limited technical workforce in this domain, and a need for a realistic entry strategy. The OECD’s five-point diagnostic (institutional framework, free-zone regime, business environment, science and innovation, infrastructure) is a ready-made checklist for any Indian state government thinking about where to start.
The 100% tax exemption is not India’s path. The DR offers a blanket 15-year holiday on essentially every tax that exists. India’s GST regime, the sunset of SEZ tax benefits, and the broader constraints of fiscal federalism make this approach impossible to replicate. But that does not make the DR’s experience irrelevant. The OECD’s own critique, that the exemptions are too generic and should be complemented with targeted incentives for capital investment and R&D, is precisely the direction India’s ISM scheme has already taken. Indian states could study how DR’s free-zone administrative process works (8 processes, 47 requirements, 24 weeks to set up) and benchmark their own single-window clearance timelines against it.
The R&D gap is a warning India should take seriously. The DR spends between 0.01% and 0.03% of GDP on R&D. It has filed exactly 2 semiconductor-related PCT patents in 23 years. FONDOCYT, the sole public R&D fund, has seen half its allocated money delayed or never disbursed. This is what happens when a country builds manufacturing capacity without a parallel investment in research and innovation. India’s situation is vastly better on this front, with a large chip design ecosystem and thousands of semiconductor patents. But at the state level, the risk is real: states racing to set up OSAT plants and semiconductor training centres may treat R&D as a second-order priority. The DR experience shows that without deliberate R&D policy, even two decades of free-zone manufacturing does not produce domestic technological capability. Indian states should build R&D incentives (tax credits, industry-academia grants, innovation clusters) into their semiconductor strategies from day one, not as an afterthought.
The workforce model deserves attention, especially on gender. The DR has about 40,000 workers in advanced manufacturing, with 45% being women. That female participation rate is remarkably high. India’s semiconductor workforce is overwhelmingly male, and the broader manufacturing sector does not come close to 45% female participation. The DR achieved this partly because its free-zone model attracted industries like medical devices and textiles that already had high female employment, and the workforce carried over into higher-value manufacturing. On the training front, the DR’s approach is familiar: a Purdue University MoU for research and academic exchange (signed 2024), and Keysight Technologies opening a Centre of Excellence at INTEC in Santo Domingo (2025). Indian states setting up semiconductor training programmes through ITIs and new institutes should study these partnerships rather than relying on standalone government training programmes disconnected from industry.
Infrastructure constraints are shared, and the DR is worse off. The DR loses 37% of generated electricity during distribution, the highest in the LAC region. Its public grid averages 19 interruptions and 24 blackout hours per month. Free-zone firms bypass this by operating as non-regulated electricity users, but the grid unreliability makes it harder for local suppliers outside the free zones to participate in semiconductor supply chains. India’s grid is significantly more reliable on average, but the specific sites chosen for semiconductor clusters (Dholera, Sanand, candidate sites in Telangana and Tamil Nadu) face their own water stress and power reliability questions. The DR’s experience reinforces what I have argued elsewhere: utility infrastructure is a first-order semiconductor siting constraint, not a background assumption.
Data Extracted
| Metric | Dominican Republic | India (for comparison) | Source |
|---|---|---|---|
| Semiconductor firms operating | 0 | 10 approved under ISM | p. 8 |
| R&D expenditure (% of GDP) | 0.01–0.03% | 0.64% | p. 77 |
| Semiconductor PCT patents (2000–2023) | 2 | ~3,000+ | p. 78 |
| Free zone corporate tax rate | 0% (15 years) | 22–25% (SEZ benefits sunset) | Table 3.3, p. 56 |
| Semiconductor-related imports (2023) | USD 253 million | ~USD 30 billion+ | p. 40 |
| Semiconductor-related exports (2023) | USD 15 million | ~USD 20 billion (design services) | p. 40 |
| Electricity distribution losses | 37% | ~20% (national average) | p. 86 |
| Advanced manufacturing workforce | ~40,000 | ~95,000 (semiconductor-specific) | p. 33 |
| Women in advanced manufacturing | 45% | ~15–20% (estimated) | p. 33 |
Source
OECD (2026), Review of the Dominican Republic’s Enabling Environment for the Semiconductor and Microelectronics Industries, OECD Publishing, Paris, https://doi.org/10.1787/0b35b5a6-en.